A gate topology used in high-frequency FET technology. In such technology, the gate length must be made very short to minimize the transit time of carriers in the channel of the device, and thus maximize the speed of operation. The narrow gate can then present a high resistance to the input signal. The resistance can be reduced by producing a gate metal structure that is T-shaped or mushroom-shaped in cross section: this produces a short dimension at the base – the contact of the gate with the semiconductor – but a large area overall, reducing the resistance along the gate. This gate topology can be produced by multilevel resist techniques to create the appropriate shape prior to metallization.