A situation in which one component of a system is unable to proceed until some other component has completed an operation. As a commonly occurring example, the basic operating time of many processors is less than the time needed to read data from the memory subsystem. In general, the processor is unable to proceed further until information that is requested from the memory has been received. To cater for this, when the processor passes the address of the data to be read to the memory controller and requests information to be read from the memory, the processor enters a wait state, performing no operations of any kind, until the memory controller signals that the data is available to the processor. See also zero-wait state.