A high-speed logic family available in the form of integrated circuits based on bipolar transistors. The fast switching speeds are achieved by means of a design that avoids driving the transistors into saturation.

The basic circuit element is based on a difference amplifier, as shown in the diagram (ignoring dashed lines). In this symmetrical circuit the combined emitter current flowing through the resistor R_e is substantially constant. If the voltage V_i is equal to V_ref then each transistor, Q₁ and Q₂, conducts by the same amount and the output is at V_ref. If V_i is increased above V_ref by more than about 0.1 volts, Q₁ will be turned on while Q₂ turns off. As a result Vo increases to V⁺. Similarly if V_i is decreased below V_ref by more than about 0.1 volts, V_o will decrease to some value largely determined by V_EE, R_e, and R_c.

ECL. Two-input ECL OR gate

By placing transistors in parallel with Q1, as shown by the dashed lines, an ECL OR gate is produced. Additional buffering is required on the gate output to provide the correct voltage swings for subsequent gate inputs.

ECL provided the highest speed of any silicon-based logic family but its high power dissipation and the need for high levels of integration mean that it has been superseded by CMOS technology.