In its simplest form, a digital electronic device that performs the operation of addition on two binary digits, the augend and the number to be added, the addend. It is therefore also known as a binary adder. This operation is exemplified by the truth table shown in the diagram, where Σ is the sum and Co is the carry. From this it can be seen that binary addition may generate a carry to subsequent stages.
A full adder has provision for inputs of addend, augend, and a carry bit and is capable of generating sum and carry outputs. These adders may be cascaded when it is desired to add binary words greater than one bit in length by connecting the carry inputs of each stage to the carry output of the previous stage.
A half-adder (see diagram) is an implementation of an adder that has provision only for input of addend and augend bits and is capable of generating sum and carry outputs. These devices cannot directly be cascaded as can full adders but may be made to perform a similar function by including additional logic gating.
See also carry lookahead, parallel adder, serial adder.