A design methodology that provides a rigorous way to design sequential digital systems, i.e. digital systems in which one activity or event – an internal state – must be completed before the next one begins. An FSM must be able to generate outputs and state transition sequences that are controlled by inputs and the current system state. It can only exist in one of 2ⁿ states, where n is equal to the number of bits in the system state. An FSM is usually specified by means of a state diagram, where circles represent the states in a system, and arcs connect reachable states. The arcs are marked with the input condition that causes the change in state, and in some cases the output values for that state transition.

State diagrams are shown overleaf for Moore and Mealy circuits. A Moore circuit is a digital sequential design, using FSMs, in which the output is a function of the state only and is independent of the external inputs. A Mealy circuit is a digital sequential design, again using FSMs, in which the output depends on both the current state and the external inputs.

Finite-state machines specified by state diagrams