One of the two major classes of transistor. It is a three-terminal semiconductor device in which the current flow through one pair of terminals, the source and the drain, is controlled or modulated by an electric field that penetrates the semiconductor; this field is introduced by the voltage applied at the third terminal, the gate (Fig. a). The resistance of the channel is controlled by the field, producing a voltage-controlled resistor.

(a) Field-effect transistor operation

The controlling field is applied to the gate electrode, but must be isolated somehow from the current flow in the channel. The method of isolation yields two basic types of field-effect transistor: the junction field-effect transistor (JFET) and the insulated-gate field-effect transistor (IGFET). In JFETs the isolation is provided by a reverse-biased p-n junction or a metal-semiconductor Schottky barrier, so the current flow across the junction from gate to channel is very small (see also MESFET). In IGFETs an insulating layer is placed between the gate electrode and the conducting channel, preventing any current flow between them. The most widely known practical example of the insulated-gate FET is the MOSFET (metal-oxide-silicon FET).

The conducting channel in JFETs is in the body of the semiconductor, and these transistors are classed as bulk-channel FETs. In MOSFETs the conducting channel lies at the surface of the silicon, at the silicon-oxide interface; these transistors are surface-channel FETs.

The FETs are generally described by the type of charge carrier that conducts the current in the channel: there are therefore p-channel FETs, where holes provide the conduction, and n-channel FETs, where electrons conduct. FETs can be further described by the nature of the channel: depletion-mode FETs have the conducting channel already present at zero gate voltage, and an appropriate voltage must be applied to close the channel, or turn off the FET; enhancement-mode FETs have no conducting path present between source and drain at zero gate voltage, and an appropriate gate voltage must be applied to open the channel. The voltage at which the channel is just becoming conducting is known as the threshold voltage, V_T. The presence or absence of the channel at zero volts gate voltage is determined by the details of the doping of the channel region of the FET. The general variation of drain current I_D with applied gate voltage V_G for the various types of FET is shown in Fig. b.

(b) Drain-current/gate-voltage relationships for FETs

The output characteristics of an n-channel FET are shown in Fig. c. These curves show the linear or triode region of operation at low values of drain-source voltage V_DS, corresponding to the voltage-controlled resistance described above, and the saturation region at higher values of V_DS. In the saturation region the FET channel is restricted in width, and the current flow cannot increase with further increases in the channel voltage V_DS. The FET behaves like a voltage-controlled current source. This is the region of operation for linear amplification applications. For digital switching applications, such as logic, the FET is switched between the ‘off’ state, below threshold, to a high-current ‘on’ state in the triode region.

(c) n-channel FET output (drain-current/drain-source voltage) characteristics