Solid-state memory that requires refreshing to keep the data active. A memory cell in DRAM generally consists of a capacitor and transistor (see diagram). The capacitor’s charge decays, due to leakage, so the system must periodically refresh the charge to maintain the value. When the address line is active, the MOS transistor acts as a closed switch. If the memory is to be read, the voltage on the capacitor is detected on the data line by a sense amplifier. If a write or refresh operation is called for, the data line becomes an input line. When the proper address turns on the MOS transistor in the DRAM cell, the capacitor can be charged or recharged from data-in.

Schematic of one DRAM memory cell