“buffered FET logic”的概念、定义、翻译、参考文献-科学参考

单词	buffered FET logic
释义	buffered FET logic [`bǝf·ǝrd ¦ef¦ē¦tē `läj·ik] ^ELECTRONICS A logic gate configuration used with gallium-arsenide field-effect transistors operating in the depletion mode, in which the level shifting required to make the input and output voltage levels compatible is achieved with Schottky barrier diodes. Abbreviated BFL.
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