| 单词 | linear-sweep delay circuit |
| 释义 | linear-sweep delay circuit [`lin·ē·ǝr ¦swēp di´lā ´sǝr·kǝt] ELECTRONICS A widely used form of linear time- delay circuit in which the input signal initiates action by a linear sawtooth generator, such as the bootstrap or Miller integrator, whose output is then compared with a calibrated direct-current reference voltage level. |
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