理学 微体系结构 释 instruction pipeline 指令流水线 处理器中实现指令级并行的技术。即把指令的处理过程分成若干个顺序的操作，由多个部件顺序重叠执行。具体来说，将每一条指令的处理过程划分为一系列顺序的操作（或者称为执行阶段），每个操作由处理器中的不同部件进行处理，并且不同部件可以并行地处理多条指令的不同操作。这样，指令流水线使得处理器可以同时处理多条指令，从而实现了指令级并行。
计算机硬件 计算机逻辑部件 释文 instruction pipeline 指令流水线
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